In certain flat panel display devices such as, for example, flat display devices utilizing cold cathodes, a gate electrode is required. In such flat panel display devices, an electron emissive cold cathode is disposed between a first electrode (e.g. a row electrode) and a second electrode (e.g. a gate electrode). By generating a sufficient voltage potential between the row electrode and the gate electrode, the electron emissive cold cathode is caused to emit electrons. In one approach, the emitted electrons are accelerated, through openings in the gate electrode, towards a display screen. In such flat panel display devices, it is desirable to have large population of the openings uniformly and consistently arranged, with sufficient spacing provided between each opening to avoid overlapping, across the surface of the gate electrode.
With reference now to Prior Art FIG. 1, a side sectional view of a conventional process step used in the formation of a prior art gate electrode is shown. As shown in Prior Art FIG. 1, a first electrode 102 has an insulating layer 104 disposed thereon. In a conventional gate electrode formation process, a non-insulating material is deposited on top of insulating layer 104 to form a very thin non-insulating layer 106 (e.g. on the order of 100 angstroms) of the non-insulating material.
With reference now to Prior Art FIG. 2, conventional gate electrode formation processes then deposit spheres, typically shown as 108, onto very thin non-insulating layer 106. Because layer 106 is very thin, it is extremely difficult for such prior art gate electrode formation processes to make very thin non-insulating layer 106 continuous. As a result, spheres 108 are not uniformly or consistently deposited across the surface of very thin non-insulating layer 106 in conventional gate electrode formation processes.
With reference next to Prior Art FIG. 3, a second layer of non-insulating material 110 is then deposited over the very thin non-insulating layer 106 and over spheres 108. As shown in Prior Art FIG. 3, second layer of non-insulating material 110 is much thicker than very thin layer of non-insulating material 106. In such prior art approaches, very thin non-insulating layer 106 together with second non-insulating layer 110 comprise the body of the gate electrode.
As shown in Prior Art FIG. 4, after the deposition of second non-insulating layer 110, spheres 108 and portions of second non-insulating layer 110 which overlie spheres 108 are removed. As a result, regions, typically shown as 112, of very thin non-insulating layer 106 have second non-insulating layer 110 removed therefrom.
Referring still to Prior Art FIG. 4, after the removal of spheres 108 and portions of second non-insulating layer 110 which overlie spheres 108, an etch step is performed. The etch step is used to form openings through very thin non-insulating layer 106. As mentioned above, spheres 108 are not uniformly or consistently disposed across the surface of very thin non-insulating layer 106 in conventional gate electrode formation processes. Consequently, conventionally formed openings in second non-insulating layer 110 and very thin non-insulating layer 106 are likewise not uniformly or consistently disposed across the surface of very thin non-insulating layer 106. In addition to forming openings through second non-insulating layer 110 and very thin non-insulating layer 106, the etch step of conventional gate electrode formation processes also substantially etches second non-insulating layer 110. The etching of second non-insulating layer 110 reduces the thickness thereof. Therefore, second non-insulating layer 110 must be deposited to a thickness which is greater than the desired thickness of the gate electrode, so that second non-insulating layer 110 will be of the desired thickness after being subjected to the etch environment. Thus, conventional gate electrode formation processes reduce the thickness of the gate electrode across the entire surface thereof when etching openings through the gate electrode, as shown in Prior Art FIG. 5.
Referring again to Prior Art FIG. 5, as yet another drawback, during etch steps of the above-described gate electrode formation process, the top surface of second non-insulating layer 110 is subjected to the etch environment. In addition to reducing the thickness of second insulating layer 110, the etch environment induces deleterious effects such as, for example, oxidation at the top surface of second non-insulating layer 110. Oxidation of the top surface of second non-insulating layer 110 complicates other processes such as the removal of subsequently deposited emitter material. Thus, conventional gate electrode formation processes subject the gate electrode to unwanted etching, and degrade the surface integrity of the gate electrode.
As still another drawback, thickness uniformity of the gate film remaining after an etch process crucially depends on the etch uniformity of the etch system employed. In large area panels, such etch non-uniformity is a major concern because it is extremely difficult to achieve sufficient etch uniformity across the large area panels. The problem of etch non-uniformity is further exacerbated when etching through submicron features.
Referring now to Prior Art FIG. 6, a schematic top view of a portion 600 of the surface of very thin non-insulating layer 106 having spheres, typically shown as 108, conventionally deposited thereon is shown. As mentioned above, during conventional gate electrode formation processes, spheres 108 are not uniformly deposited across the surface of very thin non-insulating layer 106. That is, the spacing between neighboring spheres is highly inconsistent. As shown in Prior Art FIG. 6, a particular sphere may be separated by a distance di from one neighboring sphere, separated by a distance d.sub.2 from another neighboring sphere, and separated by a distance d.sub.3 from still another neighboring sphere. Such non-uniform spacing of spheres 108 is not conducive to the formation of gates holes having small size, high density, and spatially uniform distribution.
Additionally, conventional sphere deposition processes are performed in a fluid bath. After the spheres are deposited onto the surface of very thin non-insulating layer 106 of Prior Art FIGS. 1-6, the sphere coated structure (i.e. very thin non-insulating layer 106 and the substrate underlying very thin non-insulating layer 106) is removed from the bath. However, during conventional bath removal processes, loose spheres may shift position on the surface of very thin non-insulating layer 106, and/or spheres in the fluid bath may detrimentally become deposited onto the surface of very thin non-insulating layer 106. Such unwanted sphere deposition during the removal of the substrate from the bath further renders the location of the spheres non-uniform across the surface of very thin non-insulating layer 106. The deleterious redeposition of the spheres also results in undesired clumping or grouping of the spheres on the surface of very thin non-insulating layer 106.
Many conventional gate electrode formation processes also require the use of harsh and/or caustic materials to remove the spheres from the surface of very thin non-insulating layer 106 during subsequent processing steps. Aside from being potentially damaging to other materials used in the flat panel display, such harsh and/or caustic chemicals are environmentally detrimental. As a result, these chemicals require special handling and/or disposal procedures.
Thus, a need exists for a gate electrode formation method which achieves uniform deposition of spheres. Another need exists for a gate electrode formation process which removes the substrate from a fluid bath without resulting in deleterious settling of loose spheres on the surface of the layer of the gate metal. Yet another need exists for a method which does not require the use of harsh and/or caustic materials to remove the spheres from the surface of the layer of the gate metal.